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How to generate Verilog code from Simulink model 

 July 22, 2022

By  Ayush Sengupta

What is VLSI?

VLSI is also called Very Large Scale Integration. IT is the procedure in which a complex circuit is created by connecting and combining many transistors in a single silicon semiconductor. AS software development requires programming languages, which act as a bridge between human and computer interface; similarly, in VLSI, there is a language called Verilog, which is used to create complex circuits by coding.

Semiconductor chip

Semiconductor chip

Introduction to Verilog

Verilog is a hardware description language (HDI) standardized as IEEE 1364. It is used to model electronic systems. It is most commonly used in the design verification and optimization of digital circuits at the register-transfer level of abstraction. It also verifies analogue circuits, RF Integrated circuits and mixed-signal circuits.

Verilog language supports a design at many levels of abstraction. The primary three are :

  • Behavioural level
  • Data Flow level
  • Gate level

Behavioural level:

  • It provides the highest level of abstraction provided by Verilog HDL.
  • A module can be implemented using the desired design algorithm without concern for the hardware implementation details.
  •  It specifies the circuit in terms of its expected behaviour.
  • It is the closest to a natural language description of the circuit functionality but also the most difficult to synthesize.

Dataflow level:

  • At this level, the module is designed by specifying the data flow.
  •  Looking at this design, one can realize how data flows between hardware registers and how the data is processed in the design.
  • This style is similar to logical equations. The specification is comprised of expressions made up of input signals and assigned to outputs. In most cases, such an approach can be easily translated into a structure and implemented.

Gate level:

  • The module is used in logic gates and interconnections between these gates.
  •  It resembles a schematic drawing with components connected with signals.
  • Since the logic gate is the most popular component, Verilog has a predefined set of logic gates known as primitives. Any digital circuit can be built from these primitives.
  • Lexical Tokens:

    Verilog language source text files are a channel of lexical tokens. It consists of one or more characters, and every single character is in only one token. The general tokens used by the Verilog HDL are similar to those in the programming language C.

    Programming Language. Verilog is case-sensitive. All the keywords are in lower case.

    Comments:

    There are two ways to represent the comments:

    • Comments on a single line begin with the token // and end with a carriage

    return. Ex.: //this is a single-line syntax

    • Multiline comments start with the token /* and end with */ Ex.: /*this is multiline Syntax/

    Numbers:

    • A number can be specified in binary, octal, decimal or hexadecimal format.
    • Negative numbers are represented in 2's complement numbers.
    • Verilog allowed integers, real numbers and signed & unsigned numbers.
    • The syntax is given by- <size> <radix> <value>
    • Size or unsized number can be shown using < size>, and <radix> specifies whether it is binary, octal, hexadecimal or decimal.

Identifiers:

The identifier is the name for defining an object, such as a function, module or register. Identifiers should begin with alphabetical characters or underscore characters. Ex. A_Z, a_z. Identifiers consist of alphabetic, numeric, underscore and $ characters. Their size can reach a maximum of up to 1024 characters.

Operators:

Operators are special characters used to put conditions or to operate the variables. One, two and sometimes three characters are used to perform variables' operations. Ex: >, +, ~

Verilog Keywords:

Some words have special meanings in Verilog and are called the Verilog keywords. For example, assign, case, while, wire, reg, and, or, nand, and module. They should not be used as identifiers. Verilog keywords also include compiler directives and system tasks and functions.

Gate Primitives:

The basic logic gates using one output and many inputs are used in Verilog; GATE uses one of the keywords and, nand, or, nor, xor, xnor for use in Verilog for N number of inputs and I output.

Advantages of Verilog:

  • Abstraction
  • Concurrency
  • Vendor Neutrality
  • Re-usability
  • Scalability

Get Access to
Simulink Model & Verilog Code!

Generate Verilog Code for Half Adder Circuit, Full Adder Circuit, Decoder, and Multiplexer directly from Simulink Models; Developed in MATLAB R2020a with Simulink and HDL Coder Toolbox.

Half Adder:

An adder circuit's purpose is to operate addition on two numbers. There are two inputs, augend and addend, for which two outputs are generated: the sum and the carry. It consists of two gates, the XOR gate and the AND gate. The XOR gate is responsible for getting the SUM, and the AND gate gives out the carry of the inputs.

Truth Table:

Input

Output

A

B

Sum

Carry

0

0

0

0

0

1

1

0

1

0

1

0

1

1

0

1


Simulink Circuit:

half-adder

Half-adder

Full Adder:

In the full adder circuit, the addition of 3 one-bit numbers takes place. Two of the three bits serve as the operand, while the last bit is known as the bit carried in, and it produces a two-bit output.

Truth Table:

Input

Output

A

B

Cin

Sum

Carry

0

0

0

0

0

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

1

0

0

1

0

1

0

1

0

1

1

1

0

0

1

1

1

1

1

1


Simulink Circuit:

full-adder

Full-adder

You can read more about half adder and full adder here.

Decoder:

A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the inputs and outputs are dissimilar, such as n-to-2n and binary decimal decoders. Decoding is essential in applications like data multiplexing, memory address decoding and 7-segment display. The best example of a decode circuit would be an AND gate, as when both the inputs are "High", it makes the gate output "High". The NAND gate provides an alternative to AND gate, and the output will be "Low" (0) only when all its inputs are "High". Such output is called "active low output".

Truth Table:

Input

Output

A

B

Q0

Q1

Q2

Q3

0

0

1

0

0

0

0

1

0

1

0

0

1

0

0

0

1

0

1

1

0

0

0

1


Simulink Circuit:

decoder

Decoder

Multiplexer:

A multiplexer is a device that has multiple inputs and single line output. The select lines determine which input is connected to the output and increase the amount of data sent over a network within a particular time. It is also called a data selector.

Truth Table:

Input

Output

S

I0

I1

Y

0

0

0

0

0

0

1

1

0

1

0

1

0

1

1

0

1

0

0

1

1

0

1

0

1

1

0

0

1

1

1

1


Simulink Circuit:

multiplexer

Multiplexer

Generating the VLSI Verilog Code from Simulink:

After creating the circuit in Simulink, it is necessary to develop a subsystem. To create a subsystem, we must drag and select the portion of the circuit that only consists of the logic gates. After making the subsystem, we must go to the "Apps" section and choose HDL Coder from the list. The HDL Coder interface opens, and we have to go to HDL Code Generation settings, which has the following interface:

HDL Coder Interface

HDL Coder Interface

We have to generate HDL code for the "Subsystem" only, and we will select it. We can choose the language in either Verilog or VHDL; in this case, we have preferred it to be Verilog.

You can refer to Implement Adder Circuits in Simulink a free lesson in our Simulink Fundamentals Course for a proper understanding of implementing circuits in Simulink.

Finally, we select the destination path for the folder and click on "Generate". After doing this, we can switch back to MATLAB, and get to see our file, once we click the ".v" file, as shown below:

HDL code generation result

HDL code generation result

Conclusion:

In this blog, we have learnt what VLSI is and the terms related to VLSI. Verilog is the machine language used for the computer's understanding of the creation of complex circuits using logic gates.

We have created some circuits using logic gates in Simulink, developed subsystems and then, with the help of the HDL coder, generated the Verilog code for various circuits.

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About the author 

Ayush Sengupta

Hello,
I am an Electronics and Communication Engineer who is all set to explore different fields and contribute to everything. From writing blogs to making videos to programming, there is nothing else that excites me more!

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