To understand what is a half and full adder we need to know what is an adder first.
Adder circuit is a combinational digital circuit that is used for adding two numbers. A typical adder circuit produces a sum bit (denoted by S) and a carry bit (denoted by C) as the output. Typically adders are realized for adding binary numbers but they can be also realized for adding other formats like BCD (binary coded decimal, XS-3 etc. Besides addition, adder circuits can be used for a lot of other applications in digital electronics like address decoding, table index calculation etc. Adder circuits are of two types: Half adder and Full adder.
Half adder is a combinational arithmetic circuit that adds two numbers and produces a sum bit (S) and carry bit (C) as the output. If A and B are the input bits, then sum bit (S) is the X-OR of A and B and the carry bit (C) will be the AND of A and B. From this it is clear that a half adder circuit can be easily constructed using one X-OR gate and one AND gate. Half adder is the simplest of all adder circuit, but it has a major disadvantage. The half adder can add only two input bits (A and B) and has nothing to do with the carry if there is any in the input. So if the input to a half adder have a carry, then it will be neglected it and adds only the A and B bits. That means the binary addition process is not complete and that’s why it is called a half adder. The truth table, schematic representation and XOR//AND realization of a half adder are shown in the figure below.
This type of adder is a little more difficult to implement than a half-adder. The main difference between a half-adder and a full-adder is that the full-adder has three inputs and two outputs. The first two inputs are A and B and the third input is an input carry designated as CIN. When a full adder logic is designed we will be able to string eight of them together to create a byte-wide adder and cascade the carry bit from one adder to the next.
Thus, we can implement a full adder circuit with the help of two half adder circuits. The first will half adder will be used to add A and B to produce a partial Sum. The second half adder logic can be used to add CIN to the Sum produced by the first half adder to get the final S output. If any of the half adder logic produces a carry, there will be an output carry. Thus, COUT will be an OR function of the half-adder Carry outputs. Take a look at the implementation of the full adder circuit shown below.
Implementation of Half and Full Adder in SIMULINK
First a subsystem is built which implements half adder circuit. This implementation of subsystem along with its symbol named Half Adder is shown in the figure:
XOR and AND gates can be implemented using logical operator block located at:
Simulink>>Logic and Bit operations>>Logical operators
Now Half Adder circuit can be implemented using constant blocks as input and display blocks to observe the output, as shown below:
Here A and B denote the inputs given, S stands for sum and C stands for Carry.
Similarly as Half Adder, Full Adder subsystem can also be built and implemented. The subsystem along with Symbol named Full Adder is shown below:
Where A, B and Cin are the inputs to Full adder, S stands for sum and Cout stands for carry generated at the output.
If an n-bit Full Adder is to be implemented, n blocks of Full adder can be connected consecutively. For example implementation of 4 bit Full Adder is shown in figure.
Thus Half and Full Adder circuits can be implemented in Simulink. Note that values in the constant blocks should be Boolean type only.